Technical Field
This disclosure relates to integrated circuits (ICs). More specifically, this disclosure relates to optimizing circuit design based on context-dependent useful skew estimation.
Related Art
Complex high-frequency circuits, for example, central processing units (CPUs), rely on accurately controlling clock delays to the critical path sequential elements in the circuit. Processors running at GHz frequencies utilize this technique to help balance effects from non-standard logic, like memory elements, and from logic paths with multiple stages. A custom-designed logic may be difficult to optimize and may require more skewing to achieve the highest frequency, whereas standard logic (utilizing commonly available reusable component) may often be optimized more aggressively for higher frequencies. High-frequency designs have a mixture of different types of data paths, often directly connected by a clocked sequential cell.
Conventional optimization of these designs to run at high-frequency has been a manual, custom procedure requiring deep knowledge of the architecture of the design. Existing electronic design automation (EDA) solutions do not utilize the inherent characteristics of the design (such as non-standard logic and asymmetric logic path depth) and provide minimal clock skewing, thus not achieving the highest frequencies possibly obtainable for the design architecture.